Current demands for high density and performance associated with ultra large scale integration require submicron features, increased transistor and circuit speeds and improved reliability. Such demands require formation of device features with high precision and uniformity, which in turn necessitates careful process monitoring, including frequent and detailed inspections of the devices while they are still in the form of semiconductor wafers.
A conventional in-process monitoring technique employs a two phase “inspection and review” procedure. During the first phase, the surface of the wafer is inspected at high-speed and relatively low-resolution. The purpose of the first phase is to produce a defect map showing suspected locations on the wafer having a high probability of a defect. During the second phase the suspected locations are more thoroughly analyzed. Both phases may be implemented by the same device, but this is not necessary.
The two phase inspection tool may have a single detector or multiple detectors. Multiple detector two phase inspection devices are described, by way of example, in U.S. Pat. Nos. 5,699,447, 5,982,921, and 6,178,257 whose contents are hereby incorporated herein by reference.
The contents of U.S. Pat. Nos. 7,693,323; 6,829,381 and 7,379,580 are also hereby incorporated by reference.
There exists a need for improved and more robust techniques for detecting defects in articles, and especially in semiconductor substrates.
It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.